This patent application is related to U.S. application Ser. No. 09/405,831, now issued U.S. Pat. No. 6,248,637, filed on Sep. 24, 1999, by Yu, entitled xe2x80x9cA Process for Manufacturing MOS Transistors Having Elevated Source and Drain Regions,xe2x80x9d U.S. application Ser. No. 09/397,217, filed on Sep. 16, 1999, by Yu et al., now issued U.S. Pat. No. 6,403,433, entitled xe2x80x9cSource/Drain Doping Technique for Ultra-Thin-Body SOI MOS Transistors,xe2x80x9d and U.S. application Ser. No. 09/384,121, filed on Aug. 27, 1999, by Yu, now issued U.S. Pat. No. 6,265,293, entitled xe2x80x9cCMOS Transistors Fabricated in Optimized RTA Scheme.xe2x80x9d This patent application is also related to U.S. application Ser. No. 09/609,613, filed on Jul. 5, 2000 herewith by Yu entitled, now issued U.S. Pat. No. 6,399,450, xe2x80x9cA Process for Manufacturing MOS Transistors having Elevated Source and Drain Regionsxe2x80x9d. This patent application is also related to U.S. Pat. application Ser. No. 09/781,039, filed on an even date herewith by Yu, entitled xe2x80x9cLow Temperature Process to Locally Form High-K Gate Dielectrics,xe2x80x9d U.S. Pat. application Ser. No. 09/779,985, filed on an even date herewith by Yu, entitled xe2x80x9cReplacement Gate Process for Transistor Having Elevated Source and Drain,xe2x80x9d U.S. Pat. application Ser. No. 09/779,986, filed on an even date herewith by Yu, entitled xe2x80x9cA Low Temperature Process For a Thin Film Transistor,xe2x80x9d U.S. Pat. application Ser. No. 09/779,988, filed on an even date herewith by Yu, entitled xe2x80x9cLow Temperature Process for Transistors with Elevated Source and Drain,xe2x80x9d and U.S. Pat. application Ser. No. 09/779,987, now issued U.S. Pat. No. 6,403,434, filed on an even date herewith by Yu, entitled xe2x80x9cA Process for Manufacturing MOS Transistors Having Elevated Source and Drain Regions and a High-K Gate Dielectric.xe2x80x9d All of the above patent applications are assigned to the assignee of the present application.
The present specification relates to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present application relates to a method of manufacturing integrated circuits having thin film transistors.
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistor density on ICs has been a principal focus of the microelectronics industry. An ultra-large scale integrated circuit can include over 1 million transistors. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices.
In bulk semiconductor-type devices, transistors, such as, MOSFETs are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided on the top surface between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (and thickness of the depletion layer below the inversion channel) must be scaled down to achieve superior short channel performance.
According to conventional complimentary metal oxide semiconductor (CMOS) fabrication techniques, the reduction of the depletion layer thickness is realized by a super-steep retrograded well (SSRW) ion implantation process. However, this process is limited by the diffusion of dopant atoms during subsequent thermal processes (e.g., annealing). The ion implantation process can generally only achieve an 80-nanometer or larger body thickness for a transistor. Thus, conventional fabrication techniques for bulk semiconductor type-devices cannot create transistors with a body thickness less than 80 nm.
Accordingly, bulk semiconductor-type devices can be subject to disadvantageous properties due to the relatively large body thicknesses. These disadvantageous properties include less than ideal sub-threshold voltage rolloff, short channel effects, and drain induced barrier lowering. Further still, bulk semiconductor-type devices can be subject to further disadvantageous properties such as high junction capacitance, ineffective isolation, and low saturation current. These properties are accentuated as transistors become smaller and transistor density increases on ICs.
The ULSI circuit can include CMOS field effect transistors (FETS) which have semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The source and drain regions are often silicided to reduce source/drain series resistance or contact resistance. However, as body thickness is reduced, the amount of material available for silicidation is reduced. Accordingly, large source/drain series resistance remains a considerable factor adversely affecting device performance.
The source and drain regions can be raised by selective silicon (Si) epitaxy to make connections to source and drain contacts less difficult. The raised source and drain regions provide additional material for contact silicidation processes and thereby reduce deep source/drain junction resistance and source/drain series resistance. However, the epitaxy process that forms the raised source and drain regions generally requires high temperatures exceeding 1000xc2x0 C. (e.g., 1100-1200xc2x0 C.). These high temperatures increase the thermal budget of the process and can adversely affect the formation of steep retrograde well regions and ultra shallow source/drain extensions.
The high temperatures, often referred to as a high thermal budget, can produce significant thermal diffusion which can cause shorts between the source and drain region (between the source/drain extensions). The potential for shorting between the source and drain region increases as gate lengths decrease.
Conventional SOI-type devices include an insulative substrate attached to a thin film semiconductor substrate which contains transistors similar to the MOSFET described with respect to bulk semiconductor-type devices. The transistors have superior performance characteristics due to the thin film nature of the semiconductor substrate and the insulative properties of the insulative substrate (e.g., the floating body effect). The superior performance is manifested in superior short channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current.
As transistors become smaller, the thin film semiconductor substrate also becomes thinner. The thinness of the thin film semiconductor substrate prevents effective silicidation on the thin film semiconductor substrate. Effective silicidation is necessary to form source and drain contacts. Without effective silicidation, the transistor can have large source/drain series resistances.
Typically, silicidation must consume a certain volume of the semiconductor substrate (e.g., silicon), which is not abundantly available on the thin film semiconductor substrate. The significant volume of the substrate must be consumed to appropriately make electrical contact to the source and drain regions. Accordingly, SOI-type devices are susceptible to the high series source/drain resistance which can degrade transistor saturation current and hence, the speed of the transistor. The high series resistance associated with conventional SOI CMOS technology is a major obstacle which prevents SOI technology from becoming a mainstream IC technology.
Thus, there is a need for a method of manufacturing thin film, fully depleted MOSFET ICs which has advantages over conventional bulk type devices. Further still, there is a need for a method of manufacturing a transistor which has superior short-channel performance, near ideal subthreshold swing, and high saturation current and yet is not susceptible to high series resistance and tunnel leakage current. Even further still, there is a need for a process for making a thin film transistor which has sufficient silicon for effective silicidation and includes a high-k gate dielectric. Yet further, there is a need for a fully depleted, thin film transistor with elevated source and drain regions and high-k gate dielectrics manufactured in an optimized annealing process. Yet even further, there is a need for a process flow of forming elevated source and drain regions on an SOI-substrate before forming a high-k gate dielectric.
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The integrated circuit includes a thin film transistor on a substrate. A substrate includes a thin semiconductor layer. The method includes steps of providing a sacrificial gate structure on the thin film semiconductor layer of the substrate, etching the substrate in accordance with the sacrificial gate structure, providing an amorphous semiconductor layer above the substrate and over the gate structure, removing a portion of the amorphous semiconductor layer to expose the gate structure, and forming a single crystalline material from the amorphous semiconductor material. The method also includes steps of siliciding the single crystalline material, removing the sacrificial gate structure to form an aperture, and providing a gate conductor in the aperture.
Another exemplary embodiment relates to a method of manufacturing an ultra-large scale integrated circuit including a transistor. The method includes providing a mask structure on a top surface of a thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below a top surface of the mask structure, siliciding the semiconductor material, removing the mask structure to leave an aperture, and providing a gate conductor in the aperture.
Yet another exemplary embodiment relates to a transistor including a thin film, a gate structure, source and drain regions, and a silicide layer. The gate structure includes a gate dielectric above the thin film and a gate conductor above a portion of the gate dielectric. The source and drain regions are adjacent to the gate structure. The silicide layer has a top surface above a bottom surface of the gate conductor and below a top surface of the gate conductor. The gate dielectric is at least partially above the top surface of the silicide layer.